LOGO_ADA_inc_red_explosurePrecise Timing for Best Design

Abelite Design Automation, Inc is a start-up company (Founded in February of 2012) that provides new truly statistical timing signoff tools and consulting for complex digital designs (SoC)  implemented in deep-submicron 28-to-7nm technologies.

Business Values:

  • 20-500x reduction of Timing Signoff/ECO Design Cycle
  • 8%-20% better Timing Accuracy & Excellent Correlation to Spice
  • Delivering Timing Yield requested by the designer w/o unexpected silicon failures
  • Removing Optimism & Risk in ~0.5% paths
  • Removing Pessimism, Over-designing & Over-margining in ~94% paths
  • Using truly Statistical methods of estimating Global & Local Variations from all variation sources
  • Empowered by:
    • Using truly Statistical methods of estimating Global & Local Variations from all variation sources
    • Doing Timing Closure in Whole Variation Space with thousands of Random Corners instead of using 8-126 extreme fixed PVT/RC Signoff Corners


Company & Methodology: Abelite Design Automation, Inc provides breakthrough new tools & consulting for advanced timing signoff of SoC for 28-to-7nm technologies. All tools are complimentary to current commercial STA tools & design flows. Company has developed new timing signoff paradigms  (see Abelite Profile), methodologies & statistical tools that are superior to commercially available STA/SSTA tools. The tools prevent timing violations in critical paths that lead to silicon failure & remove timing pessimism in the rest of paths. Abelite’s unique & Monte Carlo-based statistical tools offer:

  • Modeling all conceivable global/local, random/correlated sources of variations including EDA tools/flow/libraries inaccuracies/errors, PVT & geometry variations in cells, wires/vias, Double Patterning Technology (DPT), Aging Degradation (AD), Layout Dependent Effects (LDE) & FinFET
  • Estimating timing yield & power consumption
  • Achieving timing signoff with needed confidence & with taking into account the number of timing critical paths, and
  • Performing optional signoff at all needed PVT/RC/Via/AD/DPT corners

Abelite methodology prevents silicon failure while improving design performance, power & area, obtaining best QoR & reduces TAT, Costs & TTM. Methodology & tools were verified on multiple test-cases for several technology nodes. Customers are not required to change their EDA tools (like PrimeTime or Encounter Timing Analyzer/Tempus) & design flows. All Abelite tools & methodologies are unique & not available from other EDA vendors.


Abelite Design Automation, Inc
1217 Leisure Ln, Suite 11
 Walnut Creek CA 94595, USA
[email protected]
Phone: (510) 363-5421
Skype: alex.tetelbaum

Company’s website at LinkedIn:



Abelite No Spam Guarantee: We will not sell or rent your name or contact information to any 3rd party.


Past successful signoff without using advanced Abelite SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
Copyright © 2012-2014 Abelite Design Automation, Inc. All Rights Reserved.
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