Timing Report Standard

New EDA Initiative: Timing Report Standard

This project goal is to develop a Standard Timing Format (STF) for timing reports generated by STA (Static Timing Analyzer) & pseudo-SSTA (Statistical STA) tools. Currently, each STA is using its own report format that is not standardized and structured. This document has some initial thoughts and is indented to open a discussion. We plan to have detailed discussion and updates on all development activities within LinkedIn Group ATS (Advanced Timing Signoff), but we will provide brief updates in other relevant groups.

We invite all infested parties to discuss and contribute to creation of this new standard. Note that Abelite Design Automation Inc. has developed an Alpha version of STF (New Standard (V0)) and will continue to develop and coordinate all activities related to new standard. The startup is looking for participants and sponsors who are willing to support this project financially or in any other way. The website has 15 slides of initial suggestions and an example of timing report in STF. Below we briefly discuss the need for STF and some ideas.

Introduction: Current timing report generated by STA tools (from Synopsys, Cadence, Magma, Extreme DA, etc.) are not standardized like many other reports (PDF, SDF, etc.). It makes difficult to read them and process or use information in these reports. Let consider PrimeTime (Synopsys Inc.) report just as an example. Current PrimeTime report does not include all important information like used Technology, PVT/RC corners, Derating method and name of AOCV file, Information about cell voltage domains, Information about wire and vias, End cell for launch clock, Last common clock cell, etc. Additionally, this report is very difficult to read & process or place into Excel spreadsheet for analysis because: Columns are not tabulated, some columns have empty entries, User can specify different columns, Net rows may be absent, Some cells are reported in two rows and some in one and have different columns reported, Some information may be in cell or net rows and it depends which rows are present, etc. This complicates using such reports by other timing signoff tools (including Abelite) in order to improve, correct or statistically process existing data.

New Standard Report: Will use new Standard Timing Format (STF), Will be additional to current report (or eventually replace it), May become an industry standard (after discussion and acceptance), Will include all missing and important information, Will be structured (easy to read and process), May have tabulated fixed or flexible columns, Will clearly separate Data Path (DP) and Clocks, Will not include (unless specifically requested) less important but lengthily data like the common clock part, net rows and net names (if not requested), instance and net names will always the last because they may be long, and the report Will be minimum in size.

Report Sections:

  • Header: One for all paths
  • Paths (Each includes DP and Clocks sub-paths):

–      Path 1

–      Path 2

–      …

–      Path K

  • Launch Clock description (divergent part)
  • DP description
  • Capture Clock description (divergent part)
  • Optional Common Clock description
  • Path short summary

–      …

–      Path N

–      Report Summary

 

Header: (We often use some names/numbers as example to simplify formats)

  • Time stamp (date/time of report generated)
  • Tool name (STA tool and version used to generate report)
  • Design Name
  • Technology:  <32nm | 28nm | 20nm>
  • Timing Check: <max | min>
  • PVT Corner:
    – Process:  <SS | TT | FF>
    – Voltage Domains:
          –  Domain       VDD2:  0.85V
          –  Domain       VDD1:  0.8V

–      Temperature:  <-40 | 0 | 25 | 115>

  • RC/Via Corner:

–      <C_worst | RC_worst | RC_typ | C_best | RC_best>

–      <R_worst | RC_worst | RC_ty | R_best |, RC_best>

  • Die Sizes:  X=<value>um   Y=<value>um
  • Derating:

–      Example 1:

  • Method: AOCV
  • Derate values: “aocv_tables_file_name”

–      Example 2:

  • Method: OCV
  • Derate values: “{5%,6%,7%,8%}“ [==M_cell_dp,M_net_dp, M_cell_clk,M_net_clk]
  • Comment: <‘text’>
  • Notes:

–      Values in <….> are just examples of possible

–      See Example below

 

Example of Header:

 

Path K (DP & Clocks) Description (as Example):

  • Start point, end point (as current)

Startpoint: core/xbu/axu            (rising edge-triggered flip-flop clocked by cclk)

Endpoint: core/abu_/out_reg_reg_0  (rising edge-triggered flip-flop clocked by cclk)

Clock Period:  1.2ns

CC:   X=344.112um  Y=9227.664um

FF1: X=546.344um  Y=1225.222um

FF1: X=546.344um  Y=1426.234um

  • Launch Clock description—only divergent part (See next slides):

–      Column Header & cell rows

–      Path Total Delay (w/o derating)     0.47

–      Path Total Delay (with derating)    0.54

-      Complex (Hierarchical) Cells         0

-       Delay Cells number                       0

  • DP description (See next slides):

–      Column Header & cell rows

–      Path Total Delay (w/o derating)     1.01

–      Path Total Delay (with derating)    1.025

-      Complex (Hierarchical) Cells         1

-       Delay Cells number                       0

–      Data Arrival Time (DAT) 1.546

  • Capture Clock description—only divergent part (See next slides):

–      Column Header & cell rows

–      Path Total Delay (w/o derating)     0.32

–      Path Total Delay (with derating)    0.45

-      Complex (Hierarchical) Cells         0

-       Delay Cells number                       1

  • Summary:

———————————————————————

Clock reconvergence pessimism       0.062

Clock uncertainty                                0.075

Library setup time                               0.023

SLACK WITH DERATING (VIOL)          -0.080

SLACK W/O  DERATING (VIOL)          -0.022

———————————————————————

 

Template for One Path (DP, Launch or Capture Clock) Description: Cell Voltage domain, Cell type & cell/net/pin names are in separate row: It keeps report “width” reasonable and designer can read report easier. Template:

 

Notes:

  • Each cell is described in 2 rows
  • Any member (column) is optional
  • No empty (skipped) values are allowed (“0”  or “-” must be placed instead)
  • Cell Type/Pins/Name/Net row:
  • Net name (if any) is for cell output pin
  • Cell/Net values row (all numbers are float or integer):
  • Cell & net delays include derating
  • X/Y coordinates are in mm
  • One tabulation (or empty space) between any values/names
  • After data path we also add Data Arrival Time information
  • Additional columns likely to be added (after X/Y cell coordinates):
  • Edge (Rise | Fall); C (=Comment) like & | * | etc.
  • New columns will provide info on wires and vias like:
  • Via number
  • Via delay
  • Wire width
  • Wire cap
  • Etc.

 

 

Paths:

 

Report Summary (Example):

  • Total Reported Paths    54
  • Paths w/ Violations        21
  • WNS                              -0.112
  • TNS                               -1.234
  • Sorted Slacks w/ Derates

Path_Num    Slack      Derate   #HierCell   #DelCell

#23               -0.112      0.045       0                   1

#4                 -0.091      0.021        1                  0

…

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Past successful signoff with using not advanced STA and SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
Copyright © 2012-2013 Abelite Design Automation, Inc. All Rights Reserved.
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