• White Papers:
    • Corner-based Timing Signoff and What Is Next. Abstract: “The paper describes contemporary corner-based timing signoff methodology and tools and why they have problems to handle multiple global and local variations in process (transistor, wire and via parameters), voltages (including multiple V-domains that may be partially correlated), temperatures, and aging degradation during timing signoff. It discusses trends in the number of signoff corners, minimization of this number needed for signoff with avoiding a risk of silicon failure due to insufficient number of corners. The paper discusses some limitations and drawbacks of commercial STA/SSTA tools, current timing signoff methodology, optimism and pessimism of timing derating, and timing deadlock. Finally, it outlines new advanced statistical timing signoff methods that have been developed at Abelite Corporation.
    • Design for Variability and Signoff TipsAbstract: “The paper provides useful design tips and recommendations on how to handle multiple global and local variations in process (transistor, wire and via parameters), voltage and temperatures before and during timing signoff. The presentation will share our experience and knowledge that designers can use in their practice. The paper also teaches how to better use PT-SI or PT-VX, or move to Abelite advanced timing tools.” 
  • Presentations:
    • Abelite Advanced Timing vs. STA & SSTA Tools. Presented and published at  Cadence CDNLive 2013. Abstract: “This presentation shows possible ways of improving accuracy of timing derating methods in current STA tools such as Encounter (Cadence) and PrimeTime (Synopsys). It discusses why variations and Timing Verification (Signoff) become even more important for 20nm and below nodes; it includes brief review of current methods for timing derating (OCV, AOCV, LOCV, POCV, SSTA) and their limitations; it shows why it is important to improve timing derating, taking into account all variation/error factors, and variation characterization; it presents new ways of improving timing derating without introducing new STA tools and changing signoff flow. All presented methods are complementary to Encounter and PrimeTime tools and flows and allow improving accuracy of timing and overcoming current limitations and drawbacks in derating. These methods reuse original not-derated STA timing and introduce proper not-pessimistic statistical derating that covers all sources of variations and EDA tool/libraries errors. They also may find missed violations and improve design metrics (performance, timing yield, etc.); and reduce the turn-around time. The methods are pseudo-statistical or statistical by nature and separate cell, wire and via variations; include dynamic crosstalk effects; take into account number of timing critical paths and correlations within each variation source and between them. “
    • 12 OCV MythsAbstract: This presentation discusses 16 myths about global and local variations including process, voltage, temperature, interconnect, how local or On-Chip-Variation (OCV) margins (timing derates) can be justified, how OCV margin impact design performance and cost, and what are safe OCV margins. Questions are raised about trends in variations, delay sensitivity to variations, multiple sources of variations and either SSTA or AOCV tools/features can solve the existing problems in timing derating.
    • PVT-RC-Via Signoff CornersAbstract: This presentation discusses definition of timing signoff corners and their number exposure, global and local variations, multiple sources of variations beside traditional Process-Voltage-Temperature/Resistance-Capacitance (PVT/RC/Via) variations such as EDA tools and libraries inaccuracies, design flow and models simplifications. Then, traditional corners and their number are analyzed and questioned if they cover all important cases taking into account that PVT/RC/Via space is not linear and not scalable for new technology nodes, and there new complex un-linear phenomena like temperature  inversion and other. The main problem becomes how to find the minimum number of PVT/RC/VA signoff corners that can be combined with reasonable On-Chip-Variation (OCV) margins (timing derates) or Advanced OCV (AOCV) margins in order to have desired timing yield and prevent fatal silicon failures.
  • Discussions:
    • Comments on Isadore Katz Notes at DeepChipAbstract: “Dr. Tetelbaum warns on issues with corner-based timing signoff that is still used in conventional timing signoff methodology.
    • All other discussions can be found at in Group “Advanced Timing Signoff” (for Group Members only), including the following:
    • More Design & Signoff Tips to Minimize Delay Variations
    • CCS vs NLDM library delay models
    • Abelite White Paper on “Design for Variability and Signoff Tips”
    • Abelite White Paper on “Corner-based Timing Signoff and What Is Next”
    • What are the drawbacks of AOCV? What are the assumptions that are made while generating the AOCV tables that may not hold in…
    • Power Estimation During Statistical Timing Analysis
    • Aging Degradation: Should we double the signoff corner number?
    • Can timing signoff become simpler and better?
    • Timing Signoff: Risk Factor
    • Abelite Discussions Update of 10/1/2012
    • STF Project: “Improving Readability of 3-Row Path Format” (Update 5 of September 7, 2012)
    • STF Project: “Optional statistics in path and report summaries” (Update 3 of June 26, 2012)
    • Additional Data to Standard Timing Format (STF) Report, Update 2
    • New EDA Initiative: Timing Report Standard
    • A Big Obscure EDA Company ICScape

Past successful signoff without using advanced Abelite SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
Copyright © 2012-2014 Abelite Design Automation, Inc. All Rights Reserved.
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