Patents

TETELBAUM, A. Circuit Timing Analysis Incorporating the Effects of Temperature Inversion. Part 1. Patent No. US 8,645,888. February 4, 2014.

TETELBAUM, A. Intelligent Dummy Metal Fill Process For Integrated Circuits. Patent No. US 8,397,196. March 12, 2013

TETELBAUM, A., JAMANN, J., LAUBHAN, R., ZAHN, B. Implementing And Checking Electronic Circuits With Flexible Ramptime Limits And Tools For Performing The Same. Patent No. US 8,332,792. December 11, 2012

TETELBAUM, A., MOLINA, R. Method And Apparatus Of Core Timing Prediction Of Core Logic In The Chip-Level Implementation Process Through An Over-Core Window On A Chip-Level Routing Layer. Patent No. US 8,321,826. November 27, 2012.

TETELBAUM, A. Reducing Path Delay Sensitivity to Temperature Variation in Timing-Critical Paths. Patent No. US 8,225,257. July 17, 2012.

TETELBAUM, A. Circuit Timing Analysis Incorporating the Effects of Temperature Inversion. Part 1. Patent No. US 8,181,144. May 15, 2012.

TETELBAUM, A., SREEJIT CHAKRAVARTY. Electronic Design Automation Tool And Method For Optimizing The Placement Of Process Monitors In An Integrated Circuit. Patent No. US 8,010,935. August 30, 2011.

TETELBAUM, A., SREEJIT CHAKRAVARTY. System And Method For Reducing The Generation Of Inconsequential Violations Resulting From Timing Analyses. Patent No. US 7,971,169. Date of Patent: Jun. 28, 2011.

TETELBAUM, A., MOLINA, R. Method and Apparatus of Core Timing Prediction of Core Logic in the Chip Level Implementation Process through an Over-Core Window on a Chip-Level Routing Layer. Patent No. US 7,739,639 B2. Jun. 15, 2010

TETELBAUM, A., et al. Method and Computer Program for Static Timing Analysis with Delay De-Rating and Clock Conservatism Reduction. Patent No. US 7,480,881. Jan. 20, 2009

TETELBAUM, A., Method and Computer Program for Detailed Routing of an Integrated Circuit Design with Multiple Routing Rules and Net Constraints. Patent No. US 7,370,309. May 6, 2008

TETELBAUM, A., Method of Estimating a Total Path Delay in an Integrated Circuit Design with Stochastically Weighted Conservatism. Patent No. US 7,213,223. May 1, 2007

TETELBAUM, A., Method and Computer Program For Estimating Speed-Up And Slow-Down Net Delays For Integrated Circuit Design. Patent No. US 7,178,121. Feb 13, 2007

TETELBAUM, A., MBOUOMBOUO, B., Method Of Floor-planning And Cell Placement For Integrated Circuit Chip Architecture With Internal I/O Rings. Patent No. US 7,174,524. Feb 6, 2007

TETELBAUM, A., Method of Finding Critical Nets in an Integrated Circuit Design. Patent No. US 7,107,558. Sep. 12, 2006

TETELBAUM, A., Method of Clock Driven Cell Placement and Clock Tree Synthesis for Integrated Circuit Design. Patent No. US 7,039,891. May 2, 2006

TETELBAUM, A., Minimal Bends Connection Models for Wire Density Calculation. Patent No. US 7,076,406. Jul. 11, 2006

TETELBAUM, A., Method of Noise Analysis And Correction Of Noise Violations For An Integrated Circuit Design. Patent No. US 7,062,731. Jun. 13, 2006

TETELBAUM, A., Method of Automated Repair of Crosstalk Violations And Timing Violations In An Integrated Circuit Design. Patent No. US 7,062,737. Jun. 13, 2006

TETELBAUM, A., Intelligent Crosstalk Delay Estimator For Integrated Circuit Design Flow. Patent No. US 7,043,708. May 9, 2006

TETELBAUM, A., Method and Apparatus For Implementing A Co-Axial Wire In A Semiconductor Chip. Patent No. US 7,015,569. Mar. 21, 2006

TETELBAUM, A., Intelligent engine for protection against injected crosstalk delay. Patent No. US 6,948,142. Sep. 20, 2005.

TETELBAUM, A., Integrated design system and method for reducing and avoiding crosstalk. Patent No. US 6,907,590. Jun. 14, 2005.

TETELBAUM, A., Integrated design system and method for reducing and avoiding crosstalk. Patent No. US 6,907,586. Jun. 14, 2005.

TETELBAUM, A., Wire delay distributed model. Patent No. US 6,880,141. Apr.12, 2005.

TETELBAUM, A., Global Chip Interconnect. Patent No. US 6,842,042. Jan. 11, 2005.

TETELBAUM, A., Integrated Circuit Design Flow With Capacitive Margin. Patent No. US 6,810,505. Oct. 26, 2004.

TETELBAUM, A., Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit. Patent No. US 6,725,389. Apr. 20, 2004.

TETELBAUM, A., Method for Estimating Cell Porosity of Hardmacs. Patent No. US 6,611,951. Aug. 26, 2003.

TETELBAUM, A., Method of Control Cell Placement To Minimize Connection Length And Cell Delay. Patent No. US 6,609,238. Aug. 19, 2003.

TETELBAUM, A., Integrated Design System and Method for Reducing and Avoiding Crosstalk. Patent No. US 6,594,805. Jul. 15, 2003.

TETELBAUM, A., Method For Minimizing Clock Skew For An Integrated Circuit. Patent No. US 6,594,807. Jul. 15, 2003.

TETELBAUM, A., Method Of Control Cell Placement For Datapath Macros In Integrated Circuit Designs. Patent No. US 6,588,003. Jul. 1, 2003.

TETELBAUM, A., Method of Datapath Cell Placement For Bitwise and Non-Bitwise Integrated Circuit Designs. Patent No. US 6,560,761. May 6, 2003.

TETELBAUM, A., Elmore Model Enhancement. Patent No. US 6,543,038. Apr. 1, 2003.

TETELBAUM, A., Method for Estimating Porosity of Hardmacs. Patent No. US 6,532,572. Mar. 11, 2003.

TETELBAUM, A., Method Of Global Placement Of Control Cells And Hardmac Pins In A Datapath Macro For An Integrated Circuit Design. Patent No. US 6,507,937. Jan. 14, 2003.

TETELBAUM, A., Method of Clock Buffer Partitioning To Minimize Clock Skew For An Integrated Circuit Design. Patent No. US 6,502,222. Date of Patent: Dec. 31, 2002.

TETELBAUM, A., Method of Datapath Cell Placement For An Integrated Circuit. Patent No. US 6,496,967. Dec. 17, 2002.

TETELBAUM, A., Balanced Clock Placement for Integrated Circuits Containing Megacells. Patent No.: US 6,480,994. Nov. 12, 2002.

TETELBAUM, A., Pin Placement Method For Integrated Circuits. Patent No.: US 6,449,760. Sep. 10, 2002.

TETELBAUM, A., Method of Generating An Optimal Clock Buffer Set For Minimizing Clock Skew In Balanced Clock Trees. Patent No.: US 6,442,737. Aug. 27, 2002.
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