Abelite’s Profile

Market space:

  • Customers: Electronic, Telecommunication, Wireless, System Design, Computers and other companies that design complex digital systems
  • Designs & Technologies: Electronic designs and sub-micron technologies 28nm and below where reliability, timing, timing yield, design metrics and signal integrity are very critical
  • Design Platforms: ASICs, FPGAs, and timing critical IPs
  • Solutions: Providing breakthrough advanced tools, consulting, and methodology for timing signoff, modeling of variation sources, and signal integrity verification

Market opportunity: EDA companies do not provide high quality solutions in the above areas, but these areas are critical and companies need our services for 28nm and below designs

Groth opportunities: There hundreds of companies that may use our services and the demand will grow for each new technology node because impact of variations has a trend to grow

Current Timing Signoff Methodology Paradigm  vs. Abelite new Paradigms:

See full Presentation at: Abelite_vs_STA_SSTA

Main features of current Paradigm are listed below:

  • It has drawbacks that increase a risk of silicon failure and diminish design metrics
  • It is time-consuming and based on using corner-driven paradigm in spite of ever increasing corner numbers and rare occurrence of these corners:
    • It checks delays of all stages and paths at all conceivable corners and spends most time on analyzing very unlikely (or even practically not happening) corners at the expense of accurate analysis of realistic and important corners
    •  It treats all paths in the same manner  & most time is wasted on analyzing paths at corners where they never fail
    • A few really vulnerable paths may be not analyzed at all at needed and relevant corners
  • It is using simplified timing derating methods (OCV, AOCV, LOCV, POCV, etc.) in commercial STA tools like PrimeTime (Synopsys) or Encounter Timing System (Cadence)
  • Statistical STA (SSTA) tools like PT-VX (Synopsys) and Einstimer (IBM) address some issues, but are not panacea:
    • They are not truly statistical and are based on approximate, pseudo-statistical, not Monte Carlo methods
    • They perform only local variation analysis at the given global corner
    • They take into account mainly transistor process variations even though there are multiple other factors including EDA tool and libraries inaccuracies
    • They handle interconnect statically even though interconnect delay may be greater than cell delay for 28nm node and below
    • They handle correlations simplistically by using only two grades: pure random factors and 100% correlated factors
    • They have many other drawbacks, which will be discussed at our pages
  • Thus, current STA/SSTA paradigm:
    • May cause failure in few paths and a lot of pessimism in the rest of paths
    • Requires big  runtime & disk space for libraries characterization and running tools & fixing  issues at all these corners

Abelite New Paradigms:

  • 1st New paradigm: Path-driven signoff:
    • Corners are automatically selected for each critical path
    • High accuracy of all timing estimations by using advanced statistical methods for each critical path
  • 2nd New paradigm: Stage-based signoff:
    • Corner (library) confidence level C is estimated for each stage and derating is changed as needed (relaxed for most stages) to have the same required confidence level K in all stages:
      • No need to be over conservative in one stage and optimistic in other
    • Equalizing risk at individual stages:
      • If confidence level C for stage less than required K (based on number of critical paths N_critical), then stage derating is corrected. Examples:
      • If stage is 100% cell delay dominated, C ≈ PVT/AD corner confidence (>3) and derating will need no correction or even will need a slight increase (if N_critical is high)
      • Similar statement is true for 100% cell delay dominated stages
      • For typical stages derating could be relaxed to have required confidence level K
  • Implemented:
    • Explicitly in Abelite SSTA (at_true)
    • Implicitly in Abelite Monte Carlo SSTA (at_stat) by generating global  corners & local variations using provided distributions for all variation factors

Abelite Philosophy:

    • Design resources and time are limited and must be spent on analyzing and fixing timing critical paths:
      • If designers are fixing false violations in multiple stages, it becomes more difficult to fix real problems or improve design metrics (like yield, performance, power, area)
    • Doing timing signoff at whole PVT PVT/RC_wire/RC_via & aging degradation space rather than at several rare corners
    • Using powerful delay scaling in variation space
    • Taking into account all variation (and error) factors including:
      • EDA tools/libraries inaccuracies
      • Global and local variations
      • Wire geometry and temperature
      • Via geometry and temperature
      • Dynamic crosstalk, etc.
    • Handling complex correlations in variation factors
    • Using pseudo-statistical and pure statistical (Monte Carlo) methods
    • Handling timing yield and confidence level requirements

Past successful signoff without using advanced Abelite SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
Copyright ©2013-2014 Abelite Design Automation, Inc. All Rights Reserved.


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