Abelite Design Automation, Inc is a start-up company (Founded in February of 2012) that developed new tools and provides advanced consulting in timing signoff of complex digital electronic systems for deep-submicron technologies. We have a cutting edge and break-through advanced methodology and tools verified on multiple complex designs for many technology nodes. Abelite helps their customers to justify the minimum number of Process-Voltage-Temperature & Resistance-Capacitance (PVT/RC) signoff corners, On-Chip-Variation (OCV) and Advanced OCV (AOCV) timing derates & End-Point (EP) margins for Static Timing Analyzers (STA like Synopsys’s PrimeTime and Cadence’s Encounter ETS) that matches the required timing yield and risk of silicon failure. We also provide our new methodology on design for maximum profit margin. Breakthrough statistical modeling, implemented as Variation Modeling Analyzer (VMA), of all conceivable sources of variations (including EDA tools/flow and libraries inaccuracies/errors) is used to find proper timing derates and margins for current and new technologies or specific designs. Multiple Abelite timing tools (AbeliteTime ot just AT) are also used for data mining and characterization, to generate timing report summaries, minimize and clarify timing reports, collect report statistics, diagnose potential issues in cells/nets, improve slack by using correlated clock skews & statistical processing of cross-talk delta delays, compare timing reports and signoff corners. Abelite methodology allows improving design performance & robustness and decrease pessimism & turn-around time. We help our customers to reduce their OCV/AOCV/LOCV and EP margins by factor of 2-3x, eliminate false violations (in most cases more than 40% of reported violations by current STA), significantly reduce slack pessimism (up to 300ps), and have less than 8 PVT/RC/Via signoff corners even for 14-20nm technologies. Moreover, our unique methodology of classification and estimation slack for each individual path at all possible corners allows reduce maximum number of PVT/RC corners to 4 for each path.
Past successful signoff without using advanced Abelite SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
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