Letter to Customer

Using OCV/AOCV/POCV STA or even SSTA does not properly solve your variations concerns. It means that each your current design is actually at risk of failure after manufacturing. It may result in a costly re-spin for some designs and losing important business or customers. You are also likely using excessive margins for ~80% setup paths and ~60% hold paths and too many PVT/RC/Via signoff corners with all resulting drawbacks (less competiveness, longer time-to-market time, poor TAT, lost performance, etc.). No doubt that AOCV & LOCV & POCV help to address some variation issues and is much better than OCV, but there are some critical issues that will lead to both optimism (risk) & pessimism depending on clocks location and design structure and cells used. Current OCV, AOCV, LOCV & POCV produce optimistic (design with silicon failure risk) or pessimistic result because:

  • Ignore the number of timing critical paths & do not properly increase derating to limit the probability of silicon failure (1-12 paths in each design may have a missed violation according to our latest study)
  • Most “typical” paths do not need currently used OCV/AOCV/LOCV/POCV margins and the pessimism may be as high as 300ps (setup check) and 85ps (hold check).
  • New physical effects (DPT, FinFET, Aging Degradation, Multi-voltage domains) and tools add pessimism due to extreme-corner and extreme-case methodology. Like DPT (double patterning technology) will add pessimism to STA by using worst-case shift scenario for all wire segments and timing checks.
  • OCV margins, AOCV/LOCV Tables, and single random variation (for stage delay) at POCV are designed assuming some “bad” but rare scenarios in paths. Thus, they are not a good match for all situations: “typical” paths are overdesigned (pessimistically estimated) and few really worse-case paths are still at risk (optimistically estimated).

Additionally, OCV, AOCV, LOCV and POCV produce inaccurate result when:

  • Stage delays in path are distributed non-uniformly (not such a rear scenario: delay cells, memories, complex or hierarchical cells, weak or overloaded cells, etc.). Note that POCV is an exception.
  • There are complex or hierarchical cells with internal depth in cell internal paths that are ignored or difficult to take into account.
  • There are cells that have some internal built-in OCV margins (like in most memories) that will lead to double margining.
  • There are vias in nets that have a lot of resistance in current technologies and are not treated properly.
  • There are un-correlated or partially correlated voltage domains.
  • There are wire segments in different metal layers and directions and they are not treated properly.
  • There are special paths (like directly connected launch FF and capture FF) that need different margins and there is no features that can provide different margins for different path structures.
  • Different End-Point (EP) Margin may be needed for different depth N and distance D.
  • One STA run is used with the same OCV/LOCV/AOCV tables or random variation of POCV for setup and hold checks in order to minimize runtime and TAT, but actually different OCV/AOCV/LOCV tables and random factor of POCV must be used for these checks.
  • Arbitrary ratio of the cell delay to the stage delay is possible (general case).
  • Finally last but not the least. IC Compiler does not produce balanced cell/net delay clocks. It means that one clock may be cell delay dominated and another one is net delay dominated. In this case, all (most) PVT/RC/Via corners are needed to avoid silicon failures, because none or a very small (local and global) delay variation cancellation will happen between clocks. Moreover, if AOCV/LOCV tables (or box size in POCV) take into account inter-clock variation cancellation as a function of clock distance D (smaller clock distance D has smaller derates), then D does not change clock skew or slack in this case and it will lead to inaccuracy and optimism –serious risk factor even if all corners were used.
  • Etc.

Beta version of Abelite’s AT-Rite Tool based on Abelite Enhanced AOCV (EAOCV) method is based on post-processing PrimeTime timing reports and improving accuracy of derating by taking into account inter-clock correlation. It also, solves several of the above drawbacks of OCV/AOCV/LOCV such as un-uniformed cell delays in paths, complex cells, built-in margin, improving reports and summaries, etc.

Much more powerful and advanced solution is Abelite’s AT-True tool that is also based on post-processing PrimeTime timing reports and it uses a novel pseudo-statistical timing engine that really makes a difference in quality of timing results. AT-True has drawbacks too. First, it requires additional input information about variations from different sources and these variations must be studied and characterized in advance. Second, it does not have perfect (accurate) solutions to some of the above issues, because some information is not present in PrimeTime report (like wire configuration or vias). But we know and understand these issues and provide approximate solutions or, at least, mitigate possible issues. What is even more important that AT-True provides adequate and accurate solutions for most of the above issues and, thus, it makes sure that the design will be safe and not over-margined and over-designed. You will see surprisingly smaller margins for most design paths while the tool will prevent failures for really critical and challenging paths. AT-True tool does not require changing your current design flow or tools, and is a complementary tool that may be run after PrimeTime STA. You will find a lot of bonus features in AT-True like statistical handling of crosstalk delays, finding additional PVT/RC corners needed for each path, handling designs with voltage domains, scaling delays to any PVT/RC corners, re-using SPEF file for different temperatures, managing risc, reduced size and better structured report, multiple summaries, etc.

We are also developing even more advanced and truly statistical tool AT-Stat. This tool will have the following enhancements over AT-True. It uses Monte Carlo method for finding all derates in cells, wires and vias, and then uses these derates to calculate slack variations and timing yield. This feature allows obtaining much more accurate and less conservative results. It uses statistical models (like mean & sigma) for sensitivities and other parameters (mostly for cases when parameters go beyond characterization ranges); and process, power, and temperature variation maps and Spice pre-characterized tables to find all properties and sensitivities on fly. It statistically model all cell, wire, and via properties. Examples are cell input capacitances that may have multiple values as a function of cell type and ramptime. It may work for a particular design or may generate random set of designs/paths for new technologies including random layouts for wires and vias.

Comparison of different methods of handling variations in STA and SSTA tools are shown in 2 tables below.

See more details about Abelite’s tools in Beta-Tools section.

Dr. Alexander Tetelbaum

 

Cordially,

Alexander Tetelbaum

President & CEO

 

 

P.S.

Dear Visitor/Customer,

 It is my pleasure to invite you to join “Advanced Timing Signoff” Group at LinkedIn (http://www.linkedin.com). The group discusses advanced strategies and tools for timing signoff. Our main topics also include minimum number of PVT/RC/Via signoff corners, OCV AOCV and POCV timing margins (derates), current issues, challenges, and trends.  Thanks, Alex Tetelbaum

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Past successful signoff without using advanced Abelite SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
Copyright ©2013-2014 Abelite Design Automation, Inc. All Rights Reserved.

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