AbeliteTime-True Tool

  • AbeliteTime-True (AT-True) tool is using pseudo-statistical method (w/o using time-consuming Monte Carlo)
  • This tool is complementary to PrimeTime STA and allows to overcome main AOCV drawbacks that can lead to missed violations and big pessimism for about 20-70% paths
  • The tool is more accurate than AT-Rite and may use AT-Rite’s reports to feather narrow number of timing critical paths
  • It reads, post-processes, and analyzes a timing report (generated by PrimeTime or AT-Rite) and improves derating to reduce risk and to minimize pessimism by:
    • Taking into account variations in wires and vias  and statistically combining them with variations in cells
    • Taking into account number of timing critical paths & properly increase derating to limit the probability of silicon failure
    • Handling variations from multiple sources and physical phenomena:
      • Transistor process properties variations including FinFET
      • Voltage (supply, static, and dynamic) variations
      • Temperature (including T-inversion) variations in cells, wires, and vias
      • Geometry variations in wires and vias:
      • Width, Height, and Dielectric Thickness
      • DPT (Double Pattern Technology) that varies wire spacing
      • Inaccuracies in EDA tools (errors between Extraction, 3D FinFET Extraction and modeling, Delay Calculation & waveform distortion, SPICE, libraries values, & inaccuracy of AT-True tool vs. golden values or silicon)
      • Dynamic (statistical) Crosstalk delay variations
      • Aging delay effect/variation (NBTI, HCI, BTI, etc.) and performance boost
    • Handling pure random and spatially correlated variations
    • Taking into account correlations within variation factor and between them
    • Taking into account correlations due to path structure similarity (or difference). For example, two instances of the same cell type, driving strength, library (like SVT, HVT, or LVT), input ramptime and load are 100% correlated (assuming they placed next to each other). If instances have different cell types, libraries, etc. their correlation becomes smaller. Similar considerations can be made for wires (layers, directions, width, etc.) and vias. Conventional tools ignore these correlations within each sub-path (launch, data, capture) and between sub-paths.
    • Taking into account credits (pessimism/optimism) coming from libraries (signoff corners) used
    • Taking into account inter-clock correlation
    • Separately reporting all violations missed by base (ocv/aocv) tools (few paths with “bad” structures/properties).
    • Using characterization data about variations in different sources obtained by statistical methods that allow doing characterization approximately (with 20-30% accuracy) that still results in ~0.5% error  in at_true timing
    • Generating timing report with requested (by user) K-sigma level of confidence
    • Reporting level of confidence for given corner (C_sigma_corner)
    • Calculating number of paths that had slack optimism or pessimism in input report vs. the final tool report
    • Handling complex and hierarchical cells with internal depth more than one
    • Handling complex cells (like memories) with partially built-in margins
    • Handling paths with non-uniformed delay distributions in cells, wires, and vias (core feature)
    • Reducing pessimism by accounting statistically for dynamic crosstalk (for a given time to failure) at 8-10 sigma level of confidence
    • Increasing accuracy by using polynomial models (vs. traditional linear ones) for delay scaling in PVT/RC space, variation sources characterization and modeling, and global and local variations estimations.
  • AT-TRUE  has also the following advanced features and capabilities:
    • Powerful non-linear mechanism for delay scaling from given PVT/RC/T_spef corner to any other corner:
      • It allows traversing and exploring PVT/RC/T_spef space for express timing analysis. Accuracy of scaling is within 2-12% and may be not enough for signoff accuracy requirement, but is good enough for finding additional corners for each path
      • One SPEF file extracted at a fixed temperature can be re-used and scaled to any T with <0.7% accuracy
      • Allows scaling crosstalk delta corner-to-corner
    • Finding all additional corners for each path needed to identify potential timing violators. It allows running at_true once at nominal corner and then some paths may require STA re-run, but each such path will need not more than 3 additional corners.
    • Handling multiple voltage domains (V-domains), including:
      • Setting new target voltages in V-domains
      • Auto-finding and reporting only worst case voltage combination
      • Auto-analysis and reporting all possible voltage combinations in V-domains (for validation purpose)
    • Signoff Manager for running timing signoff (one session) at multiple corners with different settings and user requirements:
      •  Risk management options including clock domain dependent end-point margins
      • Signoff Flow Checker (SFC) that checks settings and inputs for each at_true run in the flow
      • Memorizing history of the signoff flow and reporting all changes between tool runs
      • Organizing reports directories and output files, and supporting regressions
      • Optional switching between hold/setup checks
    • No other conventional STA tools we know take into account:
      • Aging degradation in cells and at_true automatically decides what degradation (Beginning-Of-Life or End-Of-Life) should be used for each path and timing check. It does it for the input corner and any additional target corner where the tool estimates slack. No other EDA company has implemented an AD-solver within their STA and users will need more signoff corners or use even more conservative margins, or accept additional risk and less yield.
      • Corner libraries conservatism and optimism, which depend on timing check for the corner and corner description. The more variation factors are included into corner definition with their extreme 3-sigma values, the more conservative corner is. Note that nominal corners on contrary will show some optimism.
      • Probability of each corner occurring in PVT/RC space among all possible corners. Rare corners (with extreme combinations of global variations) will get relaxation (credit) of derating to comply with needed level of confidence in timing. Nominal and close to nominal corners will need increased derates to have required      confidence and the tool does it automatically.
      • Required level of confidence in timing analysis that depends on user’s request and number of timing critical paths
  • Additionally, it implements the following functions:
    • Generates Path Summaries. Each Summary has data for the path such as slack and skew with and without margins. Also details are provided for each sub-path (data path, common launch clock path, divergent launch clock path, common capture clock path, and divergent capture clock path). Details include sub-path total derates; path delays with and without margins; path depths; average cell and net delays and ratios; common clock cell, etc.)
    • Generates Report Summary and statistics (number of paths reported, violated  with and without margins; WNS and TNS with and without margins; total numbers of design rules violations for each rule in different sub-paths; average depth, cell and net delay, cell do stage delay ratio for each sub-path type). Reports instances and stages to be ECO fixed in order of their priority and impact on timing.
    • Generates Structured Timing Reports that can be used to copy and paste into Excel spreadsheet
  • Beta version of the tool is released:
    • It processes [500-2,500] paths per one minute
    • Cell/wire/via local variations are at level of 20% cell/wire/via delays for setup & hold (and are function of signoff corners and characterization)
    • Main differences between pseudo-STA AT-True and SSTA EinsTimer (IBM) are the following. AT-True is much faster and consider all variation factors; it consider correlated factors that may have correlation from 0 to 1 (not just 1) and correlations are taken into account within each factor and between different objects (like cells, wires, and vias) impacted by variation of the same factor (like temperature). AT-True considers and combines variations in cells, wires, vias, and EDA tools and libraries, not only cell process variations as EinsTimer. Finally, At-True estimates credits coming from used corners, handles hierarchical cells, build-in-margins, etc.
    • The below Presentation 1 (September 4, 2012)  shows comparison of AT-True (assuming Number timing critical paths equals one) vs. PrimeTime/AOCV Tool
    • The below Presentation 2 (October 2, 2012)  shows comparison of AT-True (with using real Number timing critical paths) vs. PrimeTime/AOCV Tool



Past successful signoff without using advanced Abelite SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
Copyright ©2013-2014 Abelite Design Automation, Inc. All Rights Reserved.


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