AT-Stat

Abelite Time-Stat Tool

Abstract: It is a break-through fully statistical tool to analyze timing yield, timing violations and needed ECO fixes to meet a requested yield. It uses a new design methodology paradigm of accomplishing timing signoff at the whole variation space (thousands of corners) vs. currently used corner-based paradigm with a few corners. The tool at_stat is the only known STA/SSTA tool that uses Monte Carlo method for timing signoff of complex digital systems. It is based on an advanced Monte Carlo simulator that solves runtime and memory issues while providing high accuracy of results. It takes into account global and local variability effects in cells (power, voltage, temperature, and ageing degradation), wires, and vias (main geometry properties like width, height, dialectic thickness, spacing, shift due Double Pattern Technology, and temperature) from multiple variation sources including EDA tools errors, dependent and independent voltage supplies, and correlations across variation factors. It also has a sophisticated AC/DC power estimation engine including Markov process simulator. The tool improves accuracy of timing derating methods in current STA tools such as PrimeTime (Synopsys) and Encounter Timing System or Tempus (Cadence).

 

Introduction:

Current STA/SSTA signoff methodology for digital systems is based on using multiple extreme corners. It has 6 main drawbacks:

  1. Each corner is an extreme combination of cell, wire, via variation scenarios of multiple factors (variation sources) what makes each corner pessimistic
  2. Each corner has a very small probability to occur, but violations must be fixed anyway what worsen all design metrics
  3. Typical stage will be estimated pessimistically using this rare corner what leads to over-design
  4. Multiple corners (up to 124) may be required for timing signoff what significantly increases TAT and costs
  5. Many variation sources and correlations are not captured by commercial tools
  6. Timing derating methods (OCV, AOCV, LOCV, POCV) of contemporary STA tools have multiple drawbacks that lead to inaccuracy, pessimism, and silicon risk

 

At the same time, using a less conservative corner definition (where each factor variation is less than 3-sigma) may be risky for few not-typical stages and paths, because cell- or net-delay dominated stages may require WC cell process or net process respectively. Also, so-called SSTA tools (PT-VX, Einstimer, etc.) are not truly statistical and lack many important features. They:

  • Perform only local variation analysis at the given global corner
  • Use approximate pseudo-statistical (not Monte Carlo) methods
  • Take into account mainly transistor process variations even though there are multiple other factors including EDA tool and libraries inaccuracies
  • Handle interconnect (wires & vias) statically (not statistically) even though interconnect delay may be greater than cell delay for 28nm and below.
  • Handle crosstalk delay statically (not statistically)
  • Handle correlations simplistically: Only two types of correlations are allowed–pure random factors and 100% correlated factors. This leads to inaccuracy and risk
  • Ignore voltage domains variations and inter-domain correlations
  • Do not advise users what paths to fix in order to get needed timing yield

The only right approach to properly handle global and local variations is to develop a truly statistical (Monte Carlo based) SSTA method that is outlined below and will be discussed in details on other pages. Abelite’s Philosophy is to use design engineers’ terminology to describe inputs, specifications and output results:

  • No need to have a mathematician to translate statistical timing results and interpret what all these “sigmas, quintiles, etc.” are
  • All violations to be fixed are reported by the tool and is not a designer’s responsibility to make guesses which paths with negative slack to fix
  • Input information is simple, straightforward and minimal: No heuristic settings/options/constants with unpredictable impact on results are requested from users

 

Abelite has solved two main problems to design truly statistical STA:

  • Developed an advanced theory on how statistically model all global and local correlated variations from multiple sources
  • Developed new methods of obtaining accurate timing while having acceptable runtime and memory consumption

 

Main Breakthrough Features

The most important goals and features of Abelite Statistical STA at_stat include:

  • Using a new design methodology paradigm of accomplishing timing signoff at the whole variation space (thousands of corners) vs. currently used corner-based paradigm with a few corners
  • Implementing proper statistical derating for each path that covers all sources of variations and is not pessimistic (meets a requirement to have a specified confidence level)
  • Taking into account global and local variability effects in cells (power, voltage, temperature, and ageing degradation), wires and vias (main geometry properties like width, height, dialectic thickness, spacing, shift due Double Pattern Technology, and temperature) from multiple variation sources including EDA tools errors, dependent and independent voltage supplies, and correlations within and between variation factors
  • Taking into account correlations due to path structure similarity (or difference). For example, two instances of the same cell type, driving strength, library (like SVT, HVT, or LVT), input ramptime and load are 100% correlated (assuming they placed next to each other). If instances have different cell types, libraries, etc. their correlation becomes smaller. Similar considerations can be made for wires (layers, directions, width, etc.) and vias. Conventional tools ignore these correlations within each sub-path (launch, data, capture) and between sub-paths.
  • Finding timing yield for design, statistical slack and timing derate for each path across the whole variation space vs. fixed number of corners
  • Naturally taking into account number of timing critical paths in the design
  • Estimating slack and yield at proper level of confidence
  • Generating adequate number of corners in the variation space (2.5-5K or more if needed)
  • Introducing a new paradigm to fixing violations in design: Fix the minimum number of violations to obtain a requested timing yield
  • Determining which paths in input report are timing critical: They may be not critical in the input report (e.g.  a report at nominal corner with many positive slacks), but become critical at other corners

 

New Signoff Paradigms and Methods

at_stat is a new unique tool for complex digital systems that is based on new signoff paradigms, methods and algorithms. Particularly, this is the only tool that:

  • Is truly statistical and Monte Carlo based SSTA tool in the industry
  • Is exploring the whole PVT/RC/Via/Ageing-Degradation variation space
  • Handles partially correlated (derived) voltage domains/supplies
  • Estimates timing yield of design across the whole variation (global & local) space based on investigating:
    1. The whole variation space. Recommended mode. Best input corner is Nominal
    2. A global & local variation space around a given global corner. It may be used for extreme corners investigation. It may be considered as a variation space expansion vs. current SSTA tools
  • A local variation space around a given global corner. It may be used for extreme corners investigation. It may be considered as an advanced and enhanced tool vs. current SSTA tools
  • Has very powerful and advanced delay scaling in multi-dimensional PVT/RC/Via/Ageing-Degradation delay and variation space
  • Reports accurate timing by using the nominal corner as a main input or any other corner
  • Reports instances and stages to be ECO fixed in order of their priority and impact on timing
  • May use voltage & temperature local variation maps (if known)
  • Estimates DC/AC and total power:
    1. It uses statistical information, Markov process-based simulator and more accurate RC-models
    2. Power engine takes into account cells & wires, signal/clock slews (ramptimes) & loads, voltages and frequencies of  blocks, additional temperature increase in functioning blocks, functional scenarios of block activities and power (shut offs) and clock gating
    3. It also calculates inaccuracy of all power estimates
    4.  It does power profiling, finds power hot spots, and reports peak and average power consumption for BC/NC/WC power corners for DP & CLK cells, for AC/DC power components and for scenarios, blocks, and design
  • Uses multiple Abelite proprietary acceleration methods that include but not limited to:
    1. Not running statistical engine on paths that definitely fail or pass at most extreme global corners
    2. Using less corners generated, but applying methods to estimate expected mean/sigma of calculation errors to make results safe
    3. Using parallel execution (roadmap)
  • Uses timing reports of commercial STA tools such as PrimeTime (Synopsys) and Encounter Timing System or Tempus (Cadence) as its main input, and improves accuracy of current timing derating methods
  • Beta version of the tool is released:
    • The below Presentation 1 (July 7, 2013)  shows results of study on several important metrics for hold/setup checks as a function of Number timing critical paths in the input report

 

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Past successful signoff without using advanced Abelite SSTA tools is no guarantee of future results & a risk of silicon failure is involved.
Copyright ©2013-2014 Abelite Design Automation, Inc. All Rights Reserved.

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